Conventional transistor formation processes utilizing ion-implantation to form the channel and source/drain structures do not provide the desired abrupt profiles required to support the formation of CMOS transistors with sub-0.1 micron channel lengths.
One available fabrication method and structure is the conventional ion-implanted channel formation, which acts to control Vt (threshold voltage). The problem with this process and the resulting structure is that the profiles are too deep and not sufficiently abrupt. Controlling the dimensions, and thus the performance characteristics, of the very thin layers is not practical with ion-implantation and subsequent implant anneal steps.
The delta-doped channel also provides insufficient profiles for transistors having sub-0.1 micron channel lengths. In this process, and resulting structure, an undoped epitaxial layer is formed on top of the substrate as the channel region. The problem with this process is that Vt control is essentially governed by the thickness of the undoped layer. For sub-0.1 micron channel lengths, the substrate dopants will diffuse, resulting in undesirably high Vt, unless the layer of epitaxial silicon is thick. If the epitaxial silicon layer is thick, then detrimental short-channel effects will be excessive.
What is needed is a structure, and associated method of making, that provides adequate profiles for transistors having sub-0.1 micron channel lengths.
It is with the foregoing problems in mind that the instant invention was developed.